הרב ד"ר אבי קרסנטי

A. Undergraduate and Graduate Studies

PhD – The Hebrew University of Jerusalem (HUJI)
• The Freddy & Nadine Hermann Graduate School of Applied Science
• Division of Applied Physics & Material Science
1. Microelectronics Department &
2. Electro-Optics Department

MSc – The Hebrew University of Jerusalem (HUJI)
• The Freddy & Nadine Hermann Graduate School of Applied Science
• Division of Applied Physics & Material Science
1. Microelectronics Department &
2. Electro-Optics Department

BSc – Lev Academic Center – Jerusalem College of Technology (JCT)
• Applied Physics/Electro-Optics Engineering Department

Diploma – Lev Academic Center – Jerusalem College of Technology (JCT)
• Science and Technology Teaching Department

B. Rabbinic Studies

• Rabbinic Ordination “Rav ‘Ir” (in study)
• Rabbinic Ordination “Rav Kehila” – Barkai Center for Practical Rabbinic & Community Development
• Rabbinic Ordination “Yoré-Yoré”
• Negotiation & Mediation Diploma - Israel Center for Negotiation & Mediation (ICNM)
• Serving as Rav Kehila
• Member of URFA – Union des Rabbins Francophones pour l’Alyah
• Served as Rav Kehila and Rosh Beth-Midrash during 12 years in Jerusalem
• Rabbinic Institute – Kollel Meretz leRabbanut, Mevasseret Tzion.
• Advanced Torah Studies – Yeshivat Merkaz HaRav, Jerusalem.
• Advanced Torah Studies – Yeshivat Beth-El, Beth-El.

· Dec’20 – present (5781- ): Nominated MSc Committee Member at the Faculty of Engineering.

· Oct’17 – present (5778- ): Head of the Nanotechnology Track in Applied Physics MSc.

· Oct’16 – Sep’18 (5777-5778): Head of the Applied Physics/Electro-Optics Engineering Dept.

· Oct’14 – Sep’16 (5775-5776): Head of the Applied Physics/Electro-Optics Engineering Dept.

· Aug’14 – Sep’17 (5774-5777): Head of HaEytanim Personal Empowerment Excellence Program

38. 2017 Elevated to the grade of OSA Senior Member
by the Optical Society of America Board of Directors

37. 2016 Elevated to the grade of IEEE Senior Member
Award Plaque: “…It is a great pleasure to congratulate you on your elevation to the grade of IEEE Senior member. IEEE Senior Membership is an honor bestowed only to those who have made significant contributions to the profession…”

36. 2016 Selected and listed in Who's Who in the World 33rd Edition, 2016
Award Plaque: “…limited to those individuals who have demonstrated outstanding achievement in their own fields of endeavor and who have, thereby, contributed significantly to the betterment of contemporary society”.

35. 2015 Lev Academic Center, JCT
Maximal Award for Excellence for year 2014 (paid over)

34. 2013 Lev Academic Center, JCT
Maximal Award for Excellence for year 2012 (paid over)

33. 2011 Intel HIP DRA * (Hard IP, Division Recognition Award).
Award Plaque: "For Development & Deployment of a Comprehensive HIP Reuse Done Right Infrastructure on P1269."
* DRA is Intel very high Achievement Award.

32. 2010 Intel HIP SPA (Hard IP Division, SPontaneous Award).
Award Plaque: "For your hard work on KAVE and willingness to be flexible as the requirements have been under development. The tool has resulted in high confidence deliveries of top-quality IP to HIP's customers. Your team is a real asset to HIP!"

31. 2010 Intel HIP SRA (Hard IP Division, Special Recognition Award).
Award Plaque: "For Persistence in getting through bureaucratic hurdles and producing thorough results on KAVE evaluation of Synopsys/TSMC Hard IP. Intel Values: Quality, Customer Orientation."
* SRA is Intel high Achievement Award.

30. 2010 Intel HIP SPA (Hard IP Division, SPontaneous Award) for KAVE COE69 POLO Milestone.
Award Plaque: "For your hard work on KAVE and willingness to be flexible as the requirements have been under development. The tool has resulted in high confidence deliveries of top-quality IP to HIP's customers. Your team is a real asset to HIP!"

29. 2010 Intel HIP (Hard IP Division) Award for PCH09 Ibexpeak Product Development.
Award Plaque: "In Recognition of your outstanding contribution to the development of Intel's first generation Platform Control Hub, enabling the Nehalem-based Client, Mobile and Server platforms."

28. 2009 Intel HIP (Hard IP Division) Award for X58 and X5520 Chipset Products' Development.
Award Plaque: "In Recognition of your outstanding contribution to the development of Intel's first and fastest chipset with Intel Quick Path ™ Technology, enabling Nehalem family of Platforms."

27. 2009 Intel SEG DRA * (System-on-chip Enabling Group, Division Recognition Award).
Award Plaque: "In recognition of your contribution to KAVE development & deployment, providing an efficient platform for SoC model QA, paving the way towards SoC reuse in Intel."
* DRA is Intel very high Achievement Award.
** SoC - System on Chip.

26. 2009 Intel SEG GDLA (System-on-chip Enabling Group) Award.
Award Plaque: "In recognition for your participation in the 2009 Validation Summit by developing your Video Demo. We appreciate your effort in creating a video demo. Thank you for your creative efforts and risk taking."

25. 2008 Intel SEG GDLA (System-on-chip Enabling Group) Award.
Award Plaque: "For your effort in running KAVE on the Synopsys Hard IP".

24. 2008 Intel SEG GDLA (System-on-chip Enabling Group) Award.
Award Plaque: "For the extra effort in putting together a gap-analysis assessment report for SEG-UMG tool/flow on the areas covering RC, RV, ERC, FEV and SoC checks, within just a few day notice upon the UMG contacts are established, as well as your flexibility in accommodating the travel to US for SEG-UMG F2F, and/or off-office-hour meeting time. Thank you!"

23. 2008 Intel SEG SRA * (System-on-chip Enabling Group, Special Recognition Award)
Award Plaque: "For Hard-IP Efficiency Benchmarking Study Leadership. Avi did a thorough job in investigation, Analysis & Report of Hard-IP efficiency benchmarking among several organizations within Intel. This data has been found very valuable to SEG on its way to become a major IP supplier at Intel. Doing this, Avi has demonstrated organizational awareness, business orientation, and high quality deliverables. Congratulations!"
* SRA is Intel high Achievement Award.

22. 2008 Intel DTTC * (Design & Test Technology Conference) acceptance of BLUE SKY * Methodology.
* DTTC is Intel highest Design Research & Development Conference.
** BLUE SKY - Building Latch-Up Effectiveness.

21 2008 IDF
Award Plaque: “With high respect and estimation for your huge contribution, achievement, and activity all along the years of service in the RD. Good luck in for the next milestones”.
20. 2007 Intel DEG DAA * (Digital Enterprise Group, Division Achievement Award).
Award Plaque: "For enabling successful HVM ramp of 90nm Nineveh GbE PHY, including FCMMAP 2-layer package technology, CMT mixed-signal test capability and KMO new A/T factory build-out."
* DAA is Intel very high Achievement Award.

19. 2006 Intel LAD SRA (Lan Access Division, Special Recognition Award).
Award Plaque: "For demonstrating Risk Taking & Operational Excellence: Challenging the status quo by decoupling CTE and ISBI/ZOBI requirements, and effective failure analysis resulting in $550K savings for Nineveh. Great work!"

18. 2005 Intel CQN MTABA (Corporate Quality Network, Materials Thanks A Bunch Award).
Award Plaque: "For covering and following up on Vidalia qualifications. Your diligent work is truly appreciated. And for role modeling the Intel Values: Discipline, Quality, Results Orientation, and Great Place To Work."

17. 2005 Intel CQN DRA * (Corporate Quality Network, Division Recognition Award).
Award Plaque: "For the development of QUARTO ** Methodology and Tool - a one stop shop for early QRE engagement with the design team. Impact: Discipline, Results Orientation, Q&R Leadership, Risk Taking, Quality, Customer Orientation, Great Place To Work, Data-driven Risk Assessment, Integration, Synchronization, Teamwork. The QUARTO methodology and tool were developed by Avi Karsenty to improve Silicon quality and reliability by early QRE integration into the design team. It provides a one stop shop for the Si product QRE for Pre tape out Q&R activities. QUARTO has also started its integration into the IQUAL tool"
* DRA is Intel very high Achievement Award.
** QUARTO - QUAlity & Reliability for Tape Out readiness.
16. 2005 Intel CQN DRA * (Corporate Quality Network, Division Recognition Award).
Award Plaque: "The Development of QUARTO ** to support QREs in the Pre-Silicon Development Stage of the PLC”.
* DRA is Intel very high Achievement Award.
** QUARTO - QUAlity & Reliability for Tape Out readiness.

15. 2005 Intel LAD (Lan Access Division) Award for Nineveh * Product Development.
Award Plaque: "In Appreciation For Your Contribution To The Successful Development of Nineveh Featuring Intel ® Active Management Technology 2.0.
* Nineveh - 82566DM/DC/MM/MC Gigabit Ethernet PHY".

14. 2005 Intel LAD (Lan Access Division) Award for Tekoa * and Vidalia ** Products' Development.
Award Plaque: "In Appreciation For Your Contribution To The Successful Development of Tekoa, Featuring Intel ® Active Management Technology and Vidalia.
* Tekoa - 82573E/V PCIe Gigabit Ethernet Controller First Intel ® AMT.
** Vidalia - 82573L PCIe Gigabit Ethernet Controller Low Power & Low Cost Version".

13. 2002 Intel LAD (Lan Access Division) Award for Selah Products' Development.
Award Plaque: "Selah Production - With Selah reaching 7 million units, we are proud to allocate you a Selah Souvenir. Thanks for your contribution."

12. 2001 Award for Excellence in Teaching Physics and Engineering Courses to Intel Engineers at the Intel-U (Intel University Staff).

11. 2000 Award for Excellence in Teaching Physics and Engineering Courses to Intel Engineers at the Intel-U (Intel University Staff).

10. 2000 Intel Fab8 Award.
Award Plaque: "In recognition to your Outstanding Lecture at Intel Electronics Technology Conference."

9. 2000 Nominated 1st QRE (Quality & Reliability Engineer) of the Intel Design Center – Jerusalem.

8. 1999 Intel Fab8 Award.
Award Plaque: "In recognition of your contribution to the P629 Automotive Transfer."

7. 1999 Intel SRA * (Special Recognition Award).
Award Plaque: "For successful Management of the Measurements’ Transfer from basic Analytical Tools to advanced ones."
* SRA is Intel high Achievement Award.

6. 1998 Intel SRA * (Special Recognition Award).
Award Plaque: "For Successful Engineering Management of the P653 Process Integration & Copy Exactly from US sites to Jerusalem Fab8 Analytical Tools."
* SRA is Intel high Achievement Award.

5 1997 Intel Department Recognition
Award Plaque: “Thanks for contribution and your engineering management of P653 Process, with high motivation, invested efforts, thorough work and Out-Of-The-Box creative solutions.”

4. 1997 Intel SRA * (Special Recognition Award).
Award Plaque: "For Successful Engineering Management of the P629 Process Integration & Copy Exactly from US sites to Jerusalem Fab8 Analytical Tools."
* SRA is Intel high Achievement Award.

3. 1996 Intel Department Recognition
Award Plaque: “Thanks for your contribution and your dedicated and well-organized management of the P629 Metrology JET *.”
* JET is Joined Engineering Team (Israel/US Metrology Task Force)

2. 1996 Intel Department Recognition
Award Plaque: “Thanks for your contribution and your management of the project of measurements’ optimization in the plant’s analytical tools, improving the quality and the reliability of the measurements and the significant cost reduction.”

1. 1990 Weissbort Prize for Class best Engineering Student Project of JCT.
Award Plaque: "The 'Creation of Microlenses by Microlithographic Technology' Project has been chosen by the Nomination Committee as recipient of the Weissbort Prize for An Outstanding Student Project With Excellent Industrial Potential."

03/2018 – 12/2018: NEWSIGHT IMAGING Technology Advisory Board (TAB) Senior Member

03/2010 – 10/2011: INTEL Israel Ltd (ISRAEL) ADSG / HIP / SoC / ACT Department SoC Models QA & Release Manager

03/2008 – 02/2010: INTEL Israel Ltd (ISRAEL) SEG / CDJ / DAV Department Quality Assurance & Validation Lead

05/2006 – 02/2008: INTEL Israel Ltd (ISRAEL) SEG / CDJ / DAV Department Design Automation & Validation Engineer

01/2000 – 05/2006: INTEL Israel Ltd (ISRAEL) Intel Communication Group – Jerusalem (ICGJ) 7-years Senior Quality & Reliability Engineer (QRE) of the Jerusalem Design Center (IDCj)

09/1995 –12/1999: INTEL Electronics - Jerusalem (ISRAEL) Yield Engineering Department, Division of the Metrology Laboratory Metrology Applications Engineer

06/1992-11/1992: PATIR Research & Development - Jerusalem (ISRAEL) SAGI-NAHOR Project (Summer work)

02/1991-11/1991: C.S.E.E. (Compagnie de Signaux et d’Entreprises Electriques) TRANSPORT - Chilly-Mazarin (FRANCE) Division of Transmission-Voie-Machine (TVM) Research mission for ALTEN Society.

03/1990-01/1991: SCHLUMBERGER INDUSTRIES VELIZY (FRANCE) Telemetry Department, Spatial & Aeronautic Applications Division Research mission for ALTEN Society

A. PEER-REVIEWED ARTICLES IN REFERRED JOURNALS

1. A. Karsenty, A. Sa’ar, N. Ben-Yosef, J. Shappir, "Enhanced electroluminescence in silicon-on-insulator metal-oxide-semiconductor transistors with thin silicon layer", Applied Physics Letters, Vol. 82, No. 26, pp. 4830–4832, 2003.

2. A. Karsenty, A. Chelly, "A Comparative Study of Electrical Transport Phenomena in Ultrathin vs. Nanoscale SOI MOSFETs Devices", International Journal of Electrical and Computer Engineering, Vol. 7 No. 1, pp. 66-70, 2013.

3. A. Karsenty, A. Chelly, "Modeling of the Channel Thickness Influence on Electrical Characteristics and Series Resistance in Gate-Recessed Nanoscale SOI MOSFETs", Active and Passive Electronic Components, Volume 2013, Article ID 801634, 10 pages.

4. A. Karsenty, A. Chelly, "Comparative study of NSB and UTB SOI MOSFETs Characteristics by Extraction of Series Resistance", Solid-State Electronics, Vol. 91, pp. 28-35, 2014.

5. A. Karsenty, A. Chelly, "Influence of Series Massive Resistance on Capacitance and Conductance Characteristics in Gate-recessed Nanoscale SOI MOSFETs", Active and Passive Electronic Components, Volume 2013, Article ID 813518, 11 pages.

6. A. Karsenty, A. Chelly, "Application, Modeling and Limitations of Y-function based Methods for Massive Series Resistance in Nanoscale SOI MOSFETs", Solid-State Electronics, Vol. 92, pp. 12-19, 2014.

7. A. Karsenty, A. Chelly, “Modeling of the Transfer Characteristics for High Series Resistance in Nanoscale FD SOI MOSFET Devices”, International Journal of Engineering Innovation & Research, Vol. 3, No. 1, pp. 28-34, 2014.

8. A. Karsenty, A. Chelly, "Y-Function Analysis of the Low Temperature Behavior of Ultrathin FD SOI MOSFETs", Active and Passive Electronic Components, Volume 2014 (2014), Article ID 697369, 10 pages.

9. A. Karsenty, A. Chelly, "Investigation of the Low-Temperature Behavior of FD-SOI MOSFETs in the Saturation Regime using Y and Z functions", Active and Passive Electronic Components, Volume 2014 (2014), Article ID 782417, 8 pages.

10. A. Karsenty, A. Chelly, "Usage and limitation of standard mobility models for TCAD simulation of nano-scaled FD-SOI MOSFETs”, Active and Passive Electronic Components, Volume 2015, Article ID 460416, 9 pages.

11. A. Karsenty, A. Chelly, “Anomalous Kink Effects in Low Dimensional Gate-Recessed Fully-Depleted SOI MOSFETs at Low Temperature”, NANO: Brief Reports and Reviews, Vol. 10, No. 7 (2015) 1550093 (4 pages

12. A. Karsenty, A. Chelly, “Anomalous DIBL Effect in Fully Depleted SOI MOSFETs Using Nanoscale Gate-Recessed Channel”, Active and Passive Electronic Components, Volume 2015 (2015), Article ID 609828, 5 pages.

13. A. Zev, A. Karsenty, A. Chelly, Z. Zalevsky, "Nanoscale Silicon-On-Insulator Photo-Activated Modulator Building Block for Optical Communication", IEEE Photonics Technology Letters, Vol. 28, No. 5, pp. 569-572, March 1, 2016.

14. E. Bahalul, A. Bronfeld, S. Epshtein, Y. Saban, A. Karsenty, and Y. Arieli, "Hyperspectral imaging camera using wavefront division interference," Opt. Lett. 41, 938-941 (2016).

15. A. Bennett, I. Gadassi, Z. Priel, Y. Mandelbaum, A. Karsenty, T. Luc, A. Chelly, I. Shlimak, Z. Zalevsky, “Fast Optoelectronic Responsivity of metal-oxide-semiconductor nanostructures”, Journal of Nanophotonics. 10(3), 036001 (2016).

16. Y. Mandelbaum, A. Zev, A. Chelly, Z. Zalevsky, A. Karsenty, “Study of the Photo and Thermo-Activation Mechanisms in Nanoscale SOI Modulator”, Journal of Sensors, Volume 2017 (2017), Article ID 9581976, 11 pages.

17. A. Karsenty, E. Novoselski, A. Yifrach, E. Lanzmann and Y. Arieli, “Manipulations of Wavefront Propagation: Useful Methods and Applications for Interferometric Measurements and Scanning”, Scanning, Volume 2017, Article ID 7293905, 7 pages.

18. M. Bendayan, R. Sabo, R. Zolberg, Y. Mandelbaum, A. Chelly, A. Karsenty, "Electrical control simulation of near infrared emission in SOI-MOSFET quantum well devices," Journal of Nanophotonics. 11(3), 036016 (2017).

19. Y. Mandelbaum, I. Gadasi, A. Zev, A. Chelly, Z. Zalevsky, and A. Karsenty, “Small Signals’ Study of Thermal Induced Current in Nanoscale SOI Sensor”, Journal of Sensors, Volume 2017 (2017), Article ID 1961734, 9 pages.

20. M. Karelits, Y. Mandelbaum, A. Chelly, and A. Karsenty, “Electro-Optical Study of Nanoscale Al-Si Truncated Conical Photodetector with Subwavelength Aperture”, Journal of Nanophotonics 11(4), 046021 (2017).

21. A. Karsenty, Z. Weig, S. Feldman, Y. Arieli, “Full Field Imaging Ellipsometry (FFIE) Platform using CCD Camera and Advanced Software for Simultaneous Spots’ Sensing and Measurement”, International Journal of Measurement Technologies and Instrumentation Engineering (IJMTIE), Vol. 6, Issue 1, pages 33-45, 2017.

22. A. Karsenty, Y. Lichtenstadt, S. Naeim, Y. Arieli, “Improving Interferometry Instrumentation by Mixing Stereoscopy for 2π Ambiguity Solving”, International Journal of Measurement Technologies and Instrumentation Engineering (IJMTIE) , Vol. 6, Issue 2, pages 43-55, 2017.

23. A. Karsenty and Y. Mandelbaum, “Computer Algebra Challenges in Nanotechnology: Accurate Modeling of nanoscale electro-optic devices using Finite Elements Method”, Mathematics in Computer Science 13(1-2), 117–130 (2019).

24. M. Karelits, Y. Mandelbaum, A. Chelly, A. Karsenty, “Laser beam scanning using near-field scanning optical microscopy nanoscale silicon-based photodetector”, Journal of Nanophotonics 12(3) 036002 (23 July 2018).

25. M. Bendayan, Y. Mandelbaum, G. Teller, A. Chelly, and A. Karsenty, “Probing of Quantum Energy Levels in Nanoscale Body SOI-MOSFET: Experimental and Simulation Results”, Journal of Appl. Phys. 124, 124306 (2018), pp. 124306-1-16.

26. E. Terkieltaub-Lee, Y. Albeck, and A. Karsenty, “Mode Analysis and Optimization of Split Y-Junction Sharing Very Low Index Difference”, Journal of Nanophotonics, 13(2), 026016 (22 June 2019).

27. M. Karelits, Y. Mandelbaum, Z. Zalevsky, and A. Karsenty, “Time-Spectral based Polarization-Encoding for Spatial-Temporal Super-Resolved NSOM Readout”, Nature Scientific Reports 9, 13089 (2019).

28. M. Bendayan, A. Chelly and A. Karsenty, “Quantum Physics Applied to Modern Optical MOS Transistor”, Opt. Eng. 58(9), 097106 (2019).

29. A. Karsenty, R. Mottes, “Hall Amplifier Nanoscale Device (HAND): Modeling, Simulations and Feasibility Analysis for THz Sensor”, Nanomaterials 2019, 9(11), 1618, Special Issue “Nano Fabrications of Solid-State Sensors and Sensor Systems”.

30. J. Belhassen, Z. Zalevsky, and A. Karsenty, “Optical Polarization Sensitive Ultra-Fast Switching and Photo-Electrical Device”, Nanomaterials 2019, 9(12), 1743, Special Issue “Nano Fabrications of Solid-State Sensors and Sensor Systems”.

31. M. Karelits, E. Lozitsky, A. Chelly, Z. Zalevsky and A. Karsenty, “Advanced Surface Probing using Dual-Mode NSOM-AFM Silicon-Based Photo-Sensor”, Nanomaterials 2019, 9(12), 1792, Special Issue “Nano Fabrications of Solid-State Sensors and Sensor Systems”.

32. J. Belhassen, A. Frisch, Y. Kapellner, Z. Zalevsky, and A. Karsenty, “V-groove-shaped silicon-on-insulator photopolarized activated modulator (SOIP2AM): A polarizing transistor”, Journal of Optical Society of America (JOSA) A 37(1), 46-55 (2020).

33. T. Eisenfeld and A. Karsenty, “Super High Intensity Nano Emitting (SHINE) Pixel for High Resolution and High Brightness Displays”, Journal of Nanophotonics 14(1), 016002 (7 January 2020).

34. T. Eisenfeld and A. Karsenty, “Design and Modeling of Light Emitting Nano-pixel Structure (LENS) for High Resolution Display (HRD) in Visible Range”, Nanomaterials 2020 10(2), 214.

35. E. Terkieltaub-Lee, Y. Albeck, and A. Karsenty, “Power Transfer between coupled waveguides made of different material for smooth integrated optical communication”, Journal of Nanophotonics 14(2), 026002 (7 April 2020).

36. A. Karsenty, “A Comprehensive Review of Integrated Hall Effects in Macro-, Micro, Nano-Scales and Quantum Devices”, Sensors 2020, 20(15), 4163.

37. M. Karelits, Z. Zalevsky, A. Karsenty, “Nano Polarimetry: Enhanced AFM-NSOM Triple-Mode Polarimeter Tip”, Nature Scientific Reports 10, 16201 (2020).

38. Y. Mandelbaum, R. Mottes, Z. Zalevsky, D. Zitoun, A. Karsenty, “Design of Surface Enhanced Raman Scattering (SERS) Nanosensor Array”, Sensors 2020, 20(18), 5123.

39. H. Perlman, T. Eisenfeld, A. Karsenty, “Performance Enhancement and Applications Review of Nano Light Emitting Device (LED)”, Nanomaterials 2021, 11(1), 23. Section “Nanophotonics Materials and Devices”, Special Issue “Nanophotonics for Light-Matter Interaction”.

40. Y. Mandelbaum, R. Mottes, Z. Zalevsky, D. Zitoun, A. Karsenty, “Investigations of Shape, Material and Excitation Wavelength Effects on Field Enhancement in SERS Advanced Tips”, Nanomaterials 2021, 11(1), 237. Special Issue “Application of SERS for Nanomaterials”.

41. G. Hirshfeld, Y. Garcia, G. Perepelitsa, Y. Vidal, A. Karsenty, Y. Kabessa and A. J. Agranat, “Enhanced electro-optic effect in potassium lithium tantalate niobate at the paraelectric phase near Tc”, Results in Physics (2021), Volume 23, 104059.

42. A. Chelly, J. Belhassen, A. Karsenty, “Seebeck Coefficient’s Comparative Evaluation by Cross-Examination of Time-dependent Analytical Model, Numerical Simulation and Experimental Measurement Applied to Germanium Surface”, Applied Surface Science, Volume 568, 2021, 150876.

B. PEER-REVIEWED ARTICLES IN CONFERENCE PROCEEDINGS

1. N.P. Eisenberg, A. Karsenty, J. Broder, M. Abitbol, N. Ben Yossef, "A New Process for Manufacturing Arrays of Microlenses", Proc. SPIE 1038, 6th Mtg in Israel on Optical Engineering, pp. 388-399, 1989.

2. A. Karsenty, “SUPERMAN* was there, on the Web: A new IntrAnet Metrology Learning Center for Analytical tools’ Physics' Principles, Engineering & Advanced Applications", Intel Confidential Digest IMEC’99 Proceedings **, May 1999, pp. 783-788, 1999. A+ Conference.

* SUPERMAN: Site University for Process Engineers Researching Metrology Applications on Net

** IMEC: Intel Manufacturing for Excellence Conference – Intel highest conference in Manufacturing Methods applying Physics, Chemistry and Engineering Applications.

3. A. Karsenty, T.J. Maloney, G.K. John and A. Breed, “BLUE * SKY @ Intel: Building Latch-Up Effectiveness **”, Intel Confidential Digest DTTC'08 Proceedings ***, 12 pages, March 2008. A+ Conference (only 19 articles accepted in Design Reliability).

* BLUE: Building Latch-Up Effectiveness

** This Methodology of setting smart Latch-Up Protections to circuits was adopted in Intel.

*** DTTC: Design & Test Technology Conference: Intel highest conf. in Physics/Electronics Design

4. A. Karsenty, A. Chelly, "Analytical Unified Model (AUM) and Comparative Study Of Electrical Transport Phenomena in SOI MOSFET Ultrathin (UTD) vs. Nanoscale (NSD) Devices", ICMNP 2012: International Conference on Microelectronics, Nanoelectronics and Photonics, France, Nov. 2012.

5. A. Karsenty, A. Chelly, "Nanoscale Thick FDSOI MOSFETs: A Simple Model of Abnormal Electrical Behavior at Low Temperature", 2014 IEEE 28th Convention of Electrical and Electronics Engineers in Israel (IEEEI), Eilat, 3-5 Dec. 2014, pages 1-5.

6. A. Karsenty, A. Chelly, “Design, Development and Characterization of Nanoscale SOI-MOSFET Devices towards future Optical Communication between blocks and Chips”, Proceedings of the 4th International Symposium on Energy Challenges and Mechanics (ECM4) – Working on Small Scales, Aberdeen, Scotland, UK, 11-13 August 2015.

7. A. Karsenty, “Electro-optical nano devices based on Silicon for optical communication: A Mix of opportunities for the Industry”, Oasis 5th Conference and Exhibition on Electro-Optics Proceedings, p.167, 3-4 March 2015.

8. Roi Zolberg, Roi Sabo, Avraham Chelly, Avi Karsenty, “Development, electrical, and optical characterization of nanoscale FD-SOI MOSFET devices based on quantum well structure for optical communication between chips and internal blocks”, SPIE Optics and Photonics 2015 Conference Proceedings, Session: “Nanoengineering: Fabrication, Properties, Optics, and Devices XII”, [9556-13], San Diego, USA, 9-13 August 2015.

9. A. Zev, A. Chelly, A. Karsenty, Z. Zalevsky, "Development, Simulation and Characterization of Nanoscale Silicon On Insulator Photo-Activated Modulator (SOIPAM) Hybrid Device", 2015 International Conference on Optical MEMS and Nanophotonics (OMN) Proceedings, IEEE Photonics Society, Jerusalem, Israel, 2-6 Aug. 2015.

10. A. Zev, A. Chelly, A. Karsenty, Z. Zalevsky, “Nanoscale SOI Photo-Activated Modulator Building Block towards future Optical Communication”, Optics Engineering Conference Proceedings 2016, Lev Academic Center, Optical Communication session, Jerusalem, 2 Feb. 2016.

11. A. Bennett, A. Chelly, A. Karsenty, I. Gadasi, Z. Priel, Y. Mandelbaum, T. Lu, I. Shlimak, and Z. Zalevsky, “GErmanium Optical Tunable Excited Capacitor (GEOTEC) for Fast Optoelectronic Responsivity”, Optics Engineering Conference Proceedings 2016, Lev Academic Center, Optical Communication session, Jerusalem, 2 Feb. 2016.

12. M. Bendayan, A. Chelly, A. Karsenty, “'Modeling and Simulations of MOSQWell Transistor future Building Block for Optical Communication”, 2016 IEEE International Conference on the Science of Electrical Engineering (ICSEE) Proceedings, pages 1-5, Eilat 16-18 Nov. 2016.

13. M. Bendayan, R. Sabo, R. Zolberg, Y. Mandelbaum, A. Chelly, A. Karsenty, “Dual-mode MOS SOI nanoscale transistor serving as a building block for optical communication between blocks”, Proc. SPIE 10112, Photonic and Phononic Properties of Engineered Nanostructures VII, 101122A (February 20, 2017).

14. M. Karelits, G. Hirshfeld, Y. Mandelbaum, A. Chelly, and A. Karsenty, “Nanoscale Silicon Truncated Conical Photodetector at Subwavelength Aperture for NSOM Applications”, IEEE 2017 International Conference on Optical MEMS and Nanophotonics (OMN 2017) Proceedings, Santa Fe, New Mexico, USA, August 13-17, 2017.

15. A. Karsenty and Y. Mandelbaum, “Computer algebra in nanotechnology: Modelling of Nano Electro-Optic Devices using Finite Element Method (FEM)”, Proceeding of ACA 2017 23rd Conference on Applications of Computer Algebra, Session 6: Computer Algebra for Applied Physics, p. 138, Jerusalem, July 17–21, 2017.

16. H. Brestel, Z. Zalevsky and A. Karsenty, "Enhanced Optical Tunable Excited Capacitor (EOTEC) for Faster Responsivity," 2018 IEEE International Conference on the Science of Electrical Engineering in Israel (ICSEE), Eilat, Israel, 2018, pp. 1-4.

17. M. Karelits, Y. Mandelbaum, A. Chelly and A. Karsenty, "Slit NSOM Imaging using Nanoscale Photodetector," 2018 IEEE International Conference on the Science of Electrical Engineering in Israel (ICSEE), Eilat, Israel, 2018, pp. 1-4.

18. A. Karsenty, M. Karelits, "Spectral response filtering by lateral scanning of Silicon NSOM photodetector with subwavelength aperture," OMN 2018 Conference, Proc. SPIE 11028, Optical Sensors 2019, 110281J (11 April 2019).

19. E. Terkieltaub-Lee, Y. Albeck, and A. Karsenty, “New Modes’ Analysis in LiNbO3 Split Y-Junction Wave-Guide Sharing Very Low Index Difference”, OASIS 7 2019 Conference Proceedings, Jerusalem 1–2 April, 2019.

20. M. Karelits, A. Karsenty, “NSOM Nanoscale Si-Based Advanced Photodetector for Several Scanning Configurations”, OASIS 7 2019 Conference Proceedings, Jerusalem 1–2 April, 2019.

21. M. Karelits, E. Lozitsky, Z. Zalevsky and A. Karsenty, “Dual-mode NSOM-AFM silicon-based photodetector for advanced surface scanning”, OASIS 7 2019 Conference Proceedings, Jerusalem 1–2 April, 2019.

22. Y. Mandebaum, D. Zitoun, Z. Zalevsky and A. Karsenty, “On the Chip Enhanced Raman Imager”, OASIS 7 2019 Conference Proceedings, Jerusalem 1–2 April, 2019.

23. A. Karsenty, “Pre-Manufacturing Behavior Forecasting and Modeling of Silicon Photonics Dual-Mode Devices Using Computer Algebra”, Applications of Computer Algebra (ACA) 2019 Conference, Montreal, Canada.

24. A. Karsenty, A. Chelly, M. Sinvani, H. Pinhas, O. Wagner, Y. Danan, and Z. Zalevsky, “Label Free Super-Resolved Nanoscopy: PALM-Like, STED-Like and Hybrid AFM/NSOM”, 2019 21st International Conference on Transparent Optical Networks (ICTON), Angers, France, 9-13 July 2019, pp. 1-1.

C. OTHER SCIENTIFIC PUBLICATIONS

1. Y. Werdiger, T. Mula, Z. Alfi, and A. Karsenty, “Corporate Decision Making Upgrade: An Empirical Approach Implementing a Business Engagement One-Stop-Shop Methodology and Tool”, Proceedings of the 18th Industrial Engineering and Management Conference, Tel Aviv, March 2014.

2. Y. Werdiger, T. Mula, Z. Alfi, and A. Karsenty, "Business Control and Decision Making (BCDM): A One-Stop-Shop Methodology and Tool for Accurate Business Engagement", International Journal of Engineering Innovation & Research, Vol. 3, No. 5, pp. 718-722, 2014.

3. A. Karsenty, "The Source of Aesthetics and Fibonacci Numbers in Talmud’s Tales", BDD Journal of Torah and Scholarship, Vol. 28, pp. 57-73, December 2013.

4. A. Karsenty, “Fibonacci Sequence Usage to forecast diverse Population Growth Rates”, BDD Journal of Torah and Scholarship, Vol. 31, pp. 81-95, October 2016.

5. R. Mann, A. Karsenty, “Between the 39 Labors of Shabbat and the 39 TRIZ principles: A Masterpiece of Creativity”, 24th Conference on Torah & Science Proceedings, Lev Academic Center, April 5, 2017.

Silicon Photonics devices and Photonics Integrated Circuits (PIC) are extremely desirable for the realization of integrated optical signal processing with electronic data processing. This is in tandem with efforts to develop a generation of ultrafast computers based on the combined electronic and optical signal processing on the one hand, and advanced generations of optoelectronic devices for optical communication systems on the other hand. As part of the efforts to address the need of developing such ultra-fast computers, based on combined electronic and optical signal processing, there is a need to develop a full family of new silicon nanoscale electro-optical components towards future smooth integration into the silicon microelectronics industry. To address such concerns and needs, series of new nanoscale silicon-based electro-optics devices (transistors, capacitors, photo-activated and thermo-activated modulators, sensors, waveguides…), coupling both electrical and optical properties are developed by ALEO (Advanced Laboratory of Electro-Optics) Research Team (https://www.aleo.solutions/), under Dr. Avi Karsenty leadership. Three domains of applications use these devices: 1) Optical communication in computers, 2) Advanced Near-Field Instrumentation, and 3) Spatial measurements in micro-gravity environment.

ALEO team shares advanced research collaboration with famous worldwide institutes and groups in US, such as MIT (Massachusetts Institute of Technology), Rochester University, NIST (National Institute of Standards and Technology), AIM Photonics (Advanced Integrated Manufacturing), in Europe such as Grenoble INP Phelma, and of course in Israel such as BIU (Bar-Ilan University), HUJI (Hebrew University of Jerusalem and more.